Sallen-Key Active Low-Pass Filter: Design, Build and Bench Characterisation

What this study does. The Sallen–Key topology is the workhorse second-order active filter: two resistors, two capacitors and one op-amp deliver a maximally flat Butterworth low-pass response with a −40 dB/decade roll-off. On paper. This project closes the loop between paper and bench: a student designs a unity-gain Sallen–Key low-pass with f_c = 1 kHz from the transfer-function equations, builds it twice (breadboard, then a soldered perfboard), measures its Bode response point-by-point with a function generator and dual-channel DSO, and reports how far the measured filter deviates from the design — and why.

The measurement protocol is the heart of the study. Gain = V_out/V_in is recorded at ~30 log-spaced frequencies from 20 Hz to 100 kHz; the −3 dB cut-off is found by interpolation, pass-band flatness, the least-squares roll-off slope and the square-wave ringing signature of Q are all extracted. Each sweep is repeated, and instrument limitations — DSO accuracy, generator flatness, breadboard parasitics — enter the uncertainty budget.

The deviation is then explained, not excused: every R and C is measured on the LCR/DMM before insertion, the transfer function is re-evaluated with those values, and the circuit is simulated in ngspice with both nominal and measured values. The curves — design, simulated, measured — on one Bode plot make the tolerance story visible: ±5 % resistors and ±10 % capacitors move f_c and Q exactly as the equations predict. The deliverable is a documented design-to-measurement pipeline for a real analog circuit, the skill every electronics examiner probes.

Second-order active filters are taught through transfer functions and neat textbook Bode sketches, but the connection between the equation and the oscilloscope is usually never made: students design a filter, wire it once, look at two or three frequencies, and declare success. They cannot answer the two questions every examiner and every employer asks — how far does the real circuit deviate from the design, and can you attribute that deviation quantitatively?

Attribution is the hard part. A measured cut-off that differs from nominal could come from component tolerances (predictable from the equations if the actual values are known), from breadboard parasitics, from op-amp bandwidth limits, or from measurement error — and 'it's probably tolerances' is not an answer without component-level data and a controlled comparison.

This project addresses the gap by designing one filter, measuring it properly (~30 frequencies, repeats, stated instrument accuracy), measuring its actual components before insertion, re-evaluating the design equations and an ngspice simulation with those measured values, and rebuilding it soldered to expose breadboard parasitics — producing a complete, quantitative design-versus-reality account of a real analog circuit.

Abstract

This single-member design-and-measurement study covers a 2nd-order unity-gain Sallen–Key Butterworth low-pass (f_c = 1 kHz). Designed from the transfer-function equations, built on breadboard and perfboard with a TL071 op-amp, and characterised on the bench: gain versus frequency over 20 Hz–100 kHz, interpolated −3 dB point, pass-band flatness, fitted slope and square-wave transient response. Measured component values re-evaluate the theory and feed an ngspice model, so design, simulation and measurement sit on one Bode plot with deviations attributed to tolerances and parasitics.

Introduction

Active RC filters realise precise responses without inductors, and the Sallen–Key topology (Sallen and Key, 1955) remains the standard first active filter: one op-amp as a unity-gain buffer. The design algebra runs through ω₀ = 1/√(R₁R₂C₁C₂) and Q = √(R₁R₂C₁C₂)/(C₂(R₁+R₂)); with R₁ = R₂ = R, the Butterworth condition Q = 1/√2 is met by C₁ = 2C₂ — the choice this project builds on, with standard values (R = 10 kΩ, C₁ = 22 nF, C₂ = 10 nF) evaluated honestly rather than assumed ideal.

Existing practice and the gap

Filter theory is covered in textbooks and application literature (TI's SLOA049, Active Low-Pass Filter Design), and the TL071 datasheet gives the op-amp limits — gain–bandwidth, slew rate — that bound the topology. What student reports omit is the bench audit: Bode data with stated instrument accuracy, a least-squares roll-off slope, an interpolated −3 dB point, square-wave verification of Q, components measured before insertion, and a simulation with measured values. The gap this project fills is the complete design-to-measurement chain with an uncertainty budget, answering the examiner's standard question — 'your measured f_c is off by X %, why?' — from the student's data.

Proposed study

1. Design: evaluate ω₀ and Q for R = 10 kΩ, C₁ = 22 nF, C₂ = 10 nF; predict f_c; check the TL071's gain–bandwidth headroom.
2. Measure every component (DMM for R, LCR for C); build on breadboard; verify DC point and supply decoupling.
3. Measure the Bode response: 1 V amplitude (linearity confirmed on both DSO channels), ~30 log-spaced frequencies, gain in dB; repeat the sweep once.
4. Extract interpolated f_c, pass-band flatness, least-squares slope (2–20 kHz) and the square-wave Q signature.
5. Simulate in ngspice with nominal and measured component values; overlay design, simulated and measured curves.
6. Repeat the measurement on a soldered perfboard to quantify parasitics; write the tolerance discussion.

Feasibility

• Technical: the circuit is three passives and one op-amp; the instruments — generator, dual-channel DSO, DMM, LCR meter — are standard in B.Sc electronics labs; ngspice is free.
• Economic: TL071s, resistors, capacitors and perfboard total under ₹300; the study builds two copies, so spares are naturally on hand.
• Operational: an individual student can finish in 12 weeks at 8 h/week — build and first sweep by week 4, measurement matrix by week 8, writing by 12. Breadboard contact faults (resolved by the perfboard rebuild) and stray 50 Hz pickup are the main risks.

In scope

• One filter topology (unity-gain Sallen–Key), one response family (Butterworth low-pass), one target cut-off (1 kHz), two physical builds (breadboard, perfboard) with one op-amp type (TL071).
• Frequency-domain measurement (Bode sweep), time-domain spot checks (square wave), component-level measurement of all passives.
• ngspice simulation at nominal and measured values; response extraction and plotting in Python.

Out of scope

• Higher-order cascades, Sallen–Key high-pass/band-pass variants and equal-component designs — each is a natural extension, not part of this study.
• PCB layout design and fabrication; the perfboard build is hand-soldered.
• Temperature and supply-voltage sensitivity sweeps beyond a spot check.
• Component-level ageing or measurement of the op-amp's input capacitance.

Research design: an iterative engineering-verification study — design, simulate, build, measure, re-model — with a pre-registered measurement protocol so the bench data are comparable across builds and days.

Design (Weeks 1–2): target f_c = 1 kHz, Butterworth Q = 1/√2. With R₁ = R₂ = R and C₁ = 2C₂ the unity-gain Sallen–Key gives Q = ½√(C₁/C₂) and f_c = 1/(2πR√(C₁C₂)); R = 10 kΩ, C₁ = 22 nF, C₂ = 10 nF evaluate to f_c ≈ 1.07 kHz and Q ≈ 0.742 — the deviation from the ideal pair (22 nF vs exactly 20 nF) is itself part of the tolerance story and is reported. Op-amp check: TL071 gain–bandwidth ≈ 3 MHz keeps the loop gain ample across 20 Hz–100 kHz for this Q.

Simulation before build (Week 3): ngspice netlist with nominal values, AC analysis 10 Hz–1 MHz; confirm the simulated f_c and slope; then re-run with measured values after Step 3 to complete the overlay.

Build and component audit (Week 4): every resistor (DMM) and capacitor (LCR) measured and logged; breadboard build with supply decoupling (100 nF at the TL071 rails); DC operating point verified (output ≈ 0 V, supplies ±9 to ±12 V).

Measurement protocol (Weeks 5–8): generator sine 1 V rms amplitude (linearity confirmed by comparing channel amplitudes at 1 kHz), ~30 frequencies log-spaced 20 Hz–100 kHz; at each, record V_in and V_out (DSO, amplitude measurement on screen averages), convert to dB: 20·log₁₀(V_out/V_in); full sweep repeated on a second day. Square wave 200 Hz and 1 kHz at fixed amplitude for overshoot/ringing; one spot check at ±12 V vs ±9 V supplies for supply sensitivity. All raw screen readings and settings (volts/div, time/div, bandwidth limit) logged in the bench sheet.

Analysis (Weeks 9–11): Python (NumPy, Matplotlib) builds the Bode overlay: design curve from the transfer function, ngspice nominal and measured-value AC results, measured points with repeat-spread error bars. Extract interpolated f_c (linear interpolation across the −3 dB crossing), pass-band flatness, slope from least-squares fit of dB vs log₁₀(f) between 2–20 kHz, and Q signature from square-wave overshoot. Attribute deviations: re-evaluate f_c and Q with measured component values; compare perfboard vs breadboard f_c for the parasitic contribution; quote instrument accuracy as the measurement floor.

Timeline (12 weeks): Weeks 1–2 design and procurement; Week 3 simulation; Week 4 build and component audit; Weeks 5–8 measurement matrix and perfboard rebuild; Weeks 9–11 analysis and overlay; Week 12 report, slides and viva.

The study is a verification pipeline: the design flows into a simulation and a physical build, both of which are measured, and the three responses converge into one attribution analysis.

flowchart TD
  A["Design equations: omega_0, Q, Butterworth C1 = 2 C2"] --> B["Standard values: R = 10 k, C1 = 22 nF, C2 = 10 nF"]
  B --> C["ngspice AC simulation with nominal values"]
  B --> D["Measure every R and C (DMM, LCR) and log values"]
  D --> E["Build on breadboard: TL071, decoupling, DC check"]
  E --> F["Bode sweep: ~30 log-spaced points, 20 Hz-100 kHz"]
  F --> G["Second-day repeat sweep (repeatability)"]
  F --> H["Square wave: overshoot/ringing = Q signature"]
  D --> I["ngspice re-run with measured values"]
  E --> J["Soldered perfboard rebuild"]
  J --> K["Repeat Bode sweep on perfboard"]
  C & I & G & K --> L["Overlay: design vs simulated vs measured"]
  L --> M["Attribute: tolerance, parasitics, instruments"]
  M --> N["Uncertainty budget and report"]

Measurement chain and uncertainty budget

Every gain point traces from screen readings to dB, so the budget is explicit: DSO vertical accuracy (quoted by the instrument, e.g. ±3 %) dominates the gain uncertainty; frequency is set by the generator's display and cross-checked against the DSO period; the repeat sweep quantifies day-to-day spread. Breadboard parasitics are not estimated theoretically — they are measured as the difference between the two builds, which is the honest way to attribute them.

Core computation (abridged)

H = lambda s, R, C1, C2: 1/(1 + s*(2*R*C2) + s*s*R*R*C1*C2)   # unity-gain SK LPF
fc_design = 1/(2*np.pi*R*np.sqrt(C1*C2))
gain_db = 20*np.log10(v_out/v_in)                              # from DSO readings
slope_db_dec = np.polyfit(np.log10(f_khz[2:]), gain_db[2:], 1)[0]*10
fc_measured = np.interp(-3, -gain_db[fc_region], f_khz[fc_region])  # across the crossing

Results tables to fill (no numbers are pre-filled)

• Higher orders: cascade two sections into a 4th-order Butterworth and study interstage loading and noise.
• Switchable-Q: replace the fixed value set with a dual-gang pot or switched capacitor bank and map Q continuously.
• State-variable filter: build the four-op-amp state-variable topology and compare its tuning stability against the Sallen–Key.
• Automated sweep: control the generator and read the DSO over USB with Python to turn the manual sweep into an automated measurement script.
• Noise floor: measure the filter's output noise and connect it to the resistor and op-amp noise models.
• A departmental filter teaching kit with the measured-vs-nominal overlay as its demonstration centrepiece.